Sometimes, the most profound changes in design methodology take place with only minimal awareness on the part of the end user. Altera took what it saw to be a necessary step last week in upgrading its ...

One of the key factors in the design and development of submicron chip designs is the setting of good physical and timing constraints, no matter what type of design methodology you use. Constraints ...

FPGA devices have grown to ASIC size and complexity, but traditional EDA tools and methodologies have failed to keep pace. Engineers designing high-end FPGAs are beginning to face the types of ...

In a flat design flow, placement and routing resources are always visible and available. Designers then can perform routing optimization and avoid congestion to achieve a good-quality design ...

Fig 1. As an example of today’s ASIC design complexity, IBM’s Cu-32 ASIC product offering delivers 2.9K raw gates per square millimeter. Such advanced process nodes enable SoC design teams to ...