Electronics Weekly

VHDL/Verilog training comes with free development board

Esperan is running its project-based HDL training courses through June and July. The aim, says the training company, is to allow designers to implement their project in hardware using supplied ...
Design-Reuse

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
Business Wire

Aldec and SynthWorks Deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), underscoring the ...
EDN

VHDL verification tool is open source

An open-source constrained random verification software package that uses VHDL-200 or -2008 is available for download. The free package offers a proven methodology and allows VHDL design and ...
Electronics Weekly

VHDL training course comes with free development board

Esperan is running a series of project-based HDL training courses intended to teach design skills alongside language syntax. As part of the course package the training company is offering a free ...